The present application is related to a co-pending application entitled xe2x80x9cAn Improved Capacitor In Semiconductor Chipsxe2x80x9d, filed on Feb. 10, 2000, Ser. No. 09/502,418, and assigned to the assignee of the present application. The disclosure in that co-pending application is hereby fully incorporated by reference into the present application.
1. Field of the Invention
The present invention is generally in the field of semiconductor chips. In particular, the invention is in the field of capacitors used in semiconductor chips.
2. Background Art
FIG. 1 shows a cross section of a conventional parallel plate capacitor 100. A dielectric layer 104 is shown as sandwiched between top plate 102 and bottom plate 106. Top plate 102 is typically made of conductive material such as titanium nitride while bottom plate 106 is typically made of a different conductive material such as aluminum/copper. Bottom plate 106 might rest on a dielectric layer such as inter-layer dielectric (xe2x80x9cILDxe2x80x9d) 108 which in turn rests on a metal layer or a semiconductor substrate. By way of example, FIG. 1 shows that ILD 108 rests on semiconductor substrate 110.
It is well known that the capacitance value of a parallel plate capacitor, such as parallel plate capacitor 100, is calculated by the equation:                     C        =                                            ϵ              0                        ⁢                          ϵ              r                        ⁢            A                    t                                    (                  Equation          ⁢                      xe2x80x83                    ⁢          1                )            
where ∈0 is the permittivity of the free space (∈0=8.85xc3x9710xe2x88x9214 F/cm), ∈r is the relative permittivity (also referred to as dielectric constant or xe2x80x9ckxe2x80x9d), A is the surface area of plate 102 (or plate 106) and t is the thickness of dielectric layer 104.
Given the capacitance Equation 1, device engineers can increase capacitance by either decreasing the dielectric thickness t, using material with a high dielectric constant ∈r, or increasing the surface area A. However, device engineers have to work with the physical design limitations and electrical requirements in the circuit when adjusting the variables in capacitance Equation 1 in their attempt to increase capacitance.
Device engineers need a way to increase the capacitance without taking up the limited device surface area. As shown in FIG. 1, in parallel plate capacitor 100, plates 102 and 106 are laid out in parallel to the surface of semiconductor substrate 110. The size of parallel plates 102 and 106 can be increased in order to increase the capacitance of parallel plate capacitor 100. However, it is undesirable to consume the already limited surface area of a semiconductor die for building large capacitors.
In fact, as geometries of active circuits in semiconductor dies decrease, it becomes less and less desirable to allocate large portions of semiconductor die surface area for building parallel plate capacitors such as capacitor 100. Thus, a major problem with prior art parallel plate capacitor 100 is the amount of surface area that the two plates 102 and 106 occupy.
Referring to Equation 1, since capacitance C is inversely proportional to the dielectric thickness t, another way to increase the capacitance is by decreasing the thickness of dielectric layer 104. However, process limitations such as an unacceptable increase in defect density of thin dielectrics prevent use of very thin dielectrics. Also, as dielectric layer 104 becomes thinner, capacitance of capacitor 100 increasingly becomes a function of the voltage across parallel plates 102 and 104. By decreasing the thickness of dielectric layer 104, parallel plate capacitor 100 manifests additional problems such as a low break down voltage and a high leakage current. A combination of all of these problems prevents use of very thin dielectrics in parallel plate capacitors such as capacitor 100.
Further, in a number of semiconductor applications, accurate xe2x80x9cmatchingxe2x80x9d of capacitors is necessary. Capacitors are matched if their absolute values can be determined and replicated with accuracy. With parallel plate capacitor 100, matching of capacitors is difficult since small variations in the thickness of thin dielectric 104 results in relatively large variations in the capacitance value. Moreover, due to the fact that dielectric 104 is thin and also due to the fact that top plate 102 is made of conductive material different from the conductive material of bottom plate 106, the capacitance of capacitor 100 is a relatively strong function of the voltage applied to the capacitor plates, i.e. the capacitor does not have good linearity.
Another disadvantage with present parallel plate capacitors such as capacitor 100 is that an extra mask and additional process steps are required so that dielectric 104 will be a certain thickness (for example, 100 to 1000 Angstroms). This is necessary to ensure that top plate 102 can be fabricated at a certain desired height relative to bottom plate 106. The extra mask and its associated extra processing steps increase fabrication costs of prior art parallel plate capacitor 100.
Thus, there is serious need in the art for a capacitor in semiconductor chips that has a high capacitance density, has good matching characteristics, has a high break down voltage, has good linearity and can be fabricated at reduced cost.
The present invention is structure and method for fabrication of an improved capacitor. The invention""s capacitor overcomes the present need for a capacitor having a high capacitance density, good matching characteristics, a high break down voltage, good linearity and a reduced fabrication cost in semiconductor chips.
In one embodiment, the invention""s capacitor includes a metal column comprising a number of interconnect metal segments and a number of via metal segments stacked on one another. The metal column constitutes one electrode of the invention""s capacitor. Another electrode of the invention""s capacitor is a metal wall surrounding the metal column. In one embodiment of the invention, the metal wall is fabricated from a number of interconnect metal structures and a number of via metal structures stacked on one another.
In one embodiment of the invention, the metal wall is shaped as a hexagon. In this embodiment, a tight packing arrangement is achieved by packing individual hexagonal capacitors xe2x80x9cwall to wallxe2x80x9d so as to achieve a cluster of individual hexagonal capacitors. The cluster of individual capacitors acts as a single composite capacitor.
In one embodiment, the interconnect metal and via metal are both made of copper. In another embodiment, the interconnect metal is made of copper while the via metal is made of tungsten.